1. Field of the Invention
The present invention relates to a device and a method for searching for a bit of a signal in a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor integrated circuits have become smaller and faster, and the demand for circuits of a smaller size which quickly handle data having a longer bit length, has been increasing. It is therefore necessary to also reduce the size of a bit search circuit, and to perform a high-speed bit search.
Conventional techniques employing a bit search circuit are disclosed by U.S. Pat. Nos. 4,348,741 and 5,349,681, and Japanese Patent Application (TOKUGANHEI) Nos. 2-231966 and 3-5651.
Conventionally, the bit search method shown in FIG. 1 was used. That is, data to be bit-searched, such as 0 or 1, is provided to an inverting unit 2 and a selector 3 as an input data signal 1. The input data signal inverted by the inverting unit 2 is provided to the selector 3. Accordingly, the inverted input data signal 1xe2x80x2 and the original input data signal 1 are provided to the selector 3.
At the same time, a detection type signal 4 is provided to a decoder 5, decoded by the decoder 5 together with the most significant bit of the above described input data signal 1, and transmitted to the selector 3.
The selector 3 selects either of the input data signals 1 and 1xe2x80x2 according to the information provided by the decoder 5, and outputs the selected input data signal 1 or 1xe2x80x2 to a 1 detecting unit 6. The 1 detecting unit 6 detects, for example, the bit position at which data changes from 0 to 1 within a data string included in the provided input data signal 1, and outputs the result of the detection.
FIG. 2 is a circuit diagram showing the above described bit search method. In this figure, the input data signal 1 provides a data latch 8 with data of 32 parallel bits that is synchronized with a clock signal (CLK). Additionally, the detection type signal 4 provides a signal latch 9 with a 2-bit signal that is synchronized with the same clock signal (CLK). FIG. 3 is a timing chart showing the process implemented with the conventional technique. In synchronization with the initial clock signal (CLK shown as (1) in FIG. 3), the above described input data signal 1 (D1), is latched by the data latch 8, while the detection type signal 4 (K1) is latched by the signal latch 9.
The 32-bit data latched by the data latch 8 is provided to an inverting circuit 10 corresponding to the above described inverting unit 2 and a selector circuit 13 corresponding to the selector 3, while being held by the data latch 8. The data of the most significant bit 31 of the input data signal 1 is provided to a decoder circuit 11. Also the above described detection type signal 4 latched by the signal latch 9 is provided to the decoder circuit 11, which generates a selection signal.
This decoder circuit 11 has a configuration as shown in FIG. 4A. It is composed of AND gates 11a and 11b, and an OR gate 11c. Signals are generated according to the truth values shown in FIG. 4B. By way of example, for 1 detection, the detection type signal 4 is a signal of 0, 1, and a selection signal 1 is output. For 0 detection, the detection type signal 4 is a signal of 0, 0, and a selection signal 0 is output.
In this state, for example, when the next input data signal 1 (D2) and the detection type signal 4 (K2) are provided and are synchronized with the next clock signal (CLK shown as (2) in FIG. 3), the selector circuit 13 outputs non-inverted data or inverted data to a 1 detecting circuit 12 according to the above described selection signals. If the selector circuit 13 selects non-inverted data, the 1 detecting circuit 12 detects the bit position of 1 included in the non-inverted data, and outputs a detection result R1 at the timing of the next clock signal (CLK shown as (3) in FIG. 3). If the selector circuit 13 selects inverted data, the 1 detecting circuit detects the bit position of 0 included in the inverted data, and outputs the detection result R1 at the timing of the next clock signal (CLK shown as (3) in FIG. 3).
The above described conventional method requires many clock signals (3 clock signals (CLKs 1 (1) through (3)) in the above described example), and requires a lot of time to perform a bit search. Furthermore, a bit search circuit itself becomes large, which is counter to the goal of reducing a circuit size.
An object of the present invention is to provide a bit search circuit and a bit search method, which allow a circuit size to be reduced and a bit search to be performed in a short time period.
According to the present invention, the above described object can be achieved by providing a bit search device which comprises: a selection signal generating unit for generating a selection signal; a 1 detecting unit for detecting the bit position at which data changes from 0 to 1 within an input data string in the direction from the most significant bit to the least significant bit, or from the least significant bit to the most significant bit; a 0 detecting unit for detecting the bit position at which data changes from 1 to 0 within an input data string in the direction from the most significant bit to the least significant bit or from the least significant bit to the most significant bit; and a selecting unit for selecting either of the outputs of the 1 detecting unit and the 0 detecting unit according to the selection signal output from the selection signal generating unit, and for using the selected output as a bit search output.
The selection signal generating unit generates a selection signal. Additionally, the selection signal generating unit may generate a selection signal from a detection type signal and data at a predetermined bit or bits of an input data string. The 1 detecting unit detects the bit position at which data changes from 0 to 1, for example, within 32-bit input data and in the direction from the most significant bit to the least significant bit or from the least significant bit to the most significant bit. The 0 detecting unit detects the bit position at which data changes from 1 to 0, for example, within input data of 32 bits and in the direction from the most significant bit to the least significant bit or from the least significant bit to the most significant bit. The selecting unit selects either of the data output from the 1 detecting unit and the 0 detecting unit, and uses the selected data as an output of the bit search circuit according to the present invention.
With the above described configuration, it becomes possible to generate a selection signal and to drive the 1 and 0 detection unit, for example, when one clock signal is output, and to obtain the output of a bit search circuit when the next clock signal is output. As a result, a high-speed bit search device can be created.
Additionally, according to the present invention, the above described object can be achieved by providing a bit search device which comprises: a selection signal generating unit for generating a selection signal; a change point detecting unit for detecting the bit position at which data changes within an input data string and in the direction from the most significant bit to the least significant bit or from the least significant bit to the most significant bit; and a selecting unit for selecting any of the data of bit change points, which are output from the change point detecting unit, according to the selection signal output from the selection signal generating unit, and for outputting the selected data.
Here, the change point detecting unit detects the point (position) at which data, for example, of a 32-bit data string, changes from 0 to 1 or from 1 to 0, and outputs the detected information to the selecting unit. Additionally, the selecting unit performs an output operation based on the information output from the change point detecting unit, as the bit search device according to this preferred embodiment.
With the above described configuration, a selection signal is generated and a change point (position) is detected, for example, with 1 clock signal, so that the data of the change point at which data changes can be searched quickly and the number of circuits can be reduced by using the change point detecting unit. Thus, a device size can be reduced.